Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high-level concepts as well as specific, concrete examples from real-world systems.

This second edition reflects a decade of advancements since the first edition and includes, among other more modest changes, two new chapters: one on consistency and coherence for non-CPU accelerators (with a focus on GPUs) and one that points to formal work and tools on consistency and coherence.

Vijay Nagarajan, University of Edinburgh
Vijay Nagarajan is a Reader at the School of Informatics at the University of Edinburgh. He received a Ph.D. in Computer Science from University of California, Riverside. His research interests span computer architecture, compilers, and computer systems with a focus on memory consistency models and cache coherence protocols. He is a recipient of the Intel early career faculty honour award, a PACT best paper award, and an IEEE Top Picks honorable mention. He has served (or is currently serving) on multiple program committees including ISCA, MICRO, and HPCA. He was General Chair of LCTES 2017 and is currently serving as an Associate Editor of IEEE Computer Architecture Letters (IEEE CAL).

Daniel J. Sorin, Duke University
Daniel J. Sorin is Professor of Electrical and Computer Engineering and of Computer Science at Duke University. His research interests are in computer architecture, including dependable architectures, verification-aware processor design, and memory system design. He received a Ph.D. and M.S. in electrical and computer engineering from the University of Wisconsin, and he received a BSE in electrical engineering from Duke University. He is the recipient of an NSF Career Award, and he was a Distinguished Visiting Fellow of the Royal Academy of Engineering (UK). He is the Editor-in-Chief of IEEE Computer Architecture Letters, and he is a Founder and Chief Architect of Realtime Robotics, Inc. He is the author of a previous Synthesis Lecture, Fault Tolerant Computer Architecture (2009).

Preface to the Second Edition
Preface to the First Edition
Introduction to Consistency and Coherence
Coherence Basics
Memory Consistency Motivation and Sequential Consistency
Total Store Order and the x86 Memory Model
Relaxed Memory Consistency
Coherence Protocols
Snooping Coherence Protocols
Directory Coherence Protocols
Advanced Topics in Coherence
Consistency and Coherence for Heterogeneous Systems
Specifying and Validating Memory Consistency Models and Cache Coherence
Authors' Biographies